Error Detection and Correction in an Optoelectronic Memory System
نویسندگان
چکیده
This paper describes the implementation of error detection and correction logic in the optoelectronic cache memory prototype at the University of Pittsburgh. In this project, our goal is to integrate a 3D optical memory directly into the memory hierarchy of a personal computer. As with any optical storage system, error correction is essential to maintaining acceptable system performance. We have implemented a fully pipelined, real time, decoder for 60-bit Spectral ReedSolomon code words. The decoder is implemented in reconfigurable logic, using a single Xilinx 4000-series FPGA per code word and is fully scalable using multiple FPGA’s. The current implementation operates at 33Mhz, and processes two code words in parallel per clock cycle for an aggregate data rate of 4Gb/s. We present a brief overview of the project and of Spectral Solomom codes followed by a description of our implementation and performance data.
منابع مشابه
An approach to fault detection and correction in design of systems using of Turbo codes
We present an approach to design of fault tolerant computing systems. In this paper, a technique is employed that enable the combination of several codes, in order to obtain flexibility in the design of error correcting codes. Code combining techniques are very effective, which one of these codes are turbo codes. The Algorithm-based fault tolerance techniques that to detect errors rely on the c...
متن کاملDesign and implementation of Persian spelling detection and correction system based on Semantic
Persian Language has a special feature (grapheme, homophone, and multi-shape clinging characters) in electronic devices. Furthermore, design and implementation of NLP tools for Persian are more challenging than other languages (e.g. English or German). Spelling tools are used widely for editing user texts like emails and text in editors. Also developing Persian tools will provide Persian progr...
متن کاملA Reconfigurable Parallel Signature Analyzer for Concurrent Error Correction in DRAM
An efficient strategy to utilize a parallel signature analyzer (PSA) for concurrent soft-error correction in DRAM’S is described. For a two-level w-bit, n-word memory system, the proposed technique needs only one additional chip as opposed to log, w + 2 in the conventional Hamming code. Such an error-correction circuit (ECC) significantly improves the reliability of the memory system.
متن کامل